Storage Class Memories

This project is no longer active. Information is still available below.

Non-Volatile Random Access Memories(NVRAMs) are becoming increasingly important in the storage hierarchy as the need for energy-efficient and high performance storage medium increases in both consumer and enterprise markets. The recent deployment of Solid State Disks(SSDs) has accelerated this tendency by supporting backward compatibility with block devices. For example, consumer products such as laptops and smart phones are adopting flash memory to enhance their battery life and response time replacing hard drives. For enterprises, SSDs are used as a large long-term secondary cache residing between DRAM and hard drives, or replacements for 10,000/15,000 rpm hard drives. Beyond flash memory, several other types of non-volatile memories are currently being sold or actively under development competing for the future storage or memory medium. For example, Phase Change RAM (PCRAM) promises high density and byte-addressability, but providing long-term resistance and high synchronous read/write performance is still challenging. Ferroelectric RAM (FeRAM) provides high-performance and low power consumption, but has low density and destructive reads. Other types of NVRAMs such as memristors, carbon nanotube, and Spin-Torque-Transfer RAM (STT-RAM) are under development promising superior characteristics than the ones currently on the market.

Unfortunately, despite the increasing importance of NVRAMs, storage and memory subsystems in current operating systems are not ready to adopt this technology shift yet. Different application I/O frameworks and a better interface for storage devices are required to fully utilize their performance while dealing with unique characteristics of NVRAMs. We have been investigating the object-based storage model as a way of addressing the shortfalls of the current interfaces. Through experiments on various data placement and cleaning policies in our object-based model prototype, we demonstrate that data structures in the in-device block management layer can be as efficient as that of flash-aware file systems due to the rich file system semantics enabled by an object interface. Compared to typical logical block number-to-page mapping schemes in SSDs, our object-based data allocation scheme and its cleaning policy significantly reduce the cleaning overhead. Additionally, several optimizations exploiting the existence of objects such as object-based reliability and embedding small files are adopted in our prototype, providing better reliability and space efficiency.

Besides its use as a typical I/O device, we investigate its efficiency and extensibility by designing three specialized devices: versioning flash device, byte-addressable NVRAM key-value store and Smart SSD. Smart SSD is an in-storage processing model for SSDs, enabling low-cost, energy efficient data processing leveraging their existing hardware components. In-storage processing engine and an object interface are added to the existing SSD firmware and MapReduce-style APIs are provided to user applications so users can easily define and submit I/O jobs as the same way a normal jobs are created, without knowing the specific commands. Our experiemnts based on a real SSD device shows that it can achieve both better performance and energy efficiency by avoiding using host bandwidth and computing resources.

Computer systems that deploy Byte-addressable NVMs in the place of DRAM can leverage their non-volatility on the main memory level, however need to take into account that processor caches remain volatile. As a result, the integrity of persistent data structures after an unclean shutdown remains a major concern. Existing failure-consistency mechanisms such as logging and shadow paging, which are designed for the traditional disk-based two-tier I/O model, impose significant performance and energy overheads by writing extra data into the BNVM. We must re-design the failure-consistency mechanisms to better take advantage of the BNVM-based, single-level storage. 


For work focusing specifically on operating system support for byte-addressable non-volatile memory, see Operating System Support for NVM.


Shadow Sub-Paging: The goal for this project is to reduce the number of writes to NVRAM for better performance, energy efficiency and endurance with a failure-consistency mechanism especially designed for NVRAM systems. We’ve built a prototype to demonstrate the efficiency of SSP.  We are looking into solutions to overcome the limitation of current design: 1) high hardware overhead and 2) limited write set.

We are working on a system to allow various methods of addressing objects stored across the memory hierarchy in a flat object store. Objects will have no organizational structure other than the structure that is given to them by their name resolvers. Names can vary based on name resolver, and can range from queries to a simple one to one relation from a name to an object. This flexibility allows for existing storage mechanisms, such as file systems, to be implemented on top of a flat object store. Instead of forcing organization on these objects through a hierarchal file system like interface, they will be presented through the use of flexible name resolvers, which will give objects organization through programmatic definition.

Another project under development is an object based storage device for a byte-addressable non-volatile memory and an object-based versioning flash device. The goal for the NVRAM object storage is to provide an efficient wear-leveling and space management policy while minimizing the computational overheads in its critical path. Versioning flash device is taking advantage of the out-of-order writing requirement in flash storages to provide a low-overhead versioning.

Additionally, we are looking into the latency issues in SSD storage systems. Guaranteeing an SLA in SSD storage systems has been an issue, because latencies of SSDs are not easily predictable. As they have more program/erase cycles, the performance of SSDs also decrease, because its program and erase operations take a longer time to be stabilized. We are investigating several design challenges to make the latencies predictable at both application and device levels, and dynamically adjust the resource allocations to meet the requirement.

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Last modified 13 Oct 2022