CXL SIG (Disaggregated Memory)
In that open forum with current1 (and future2, hopefully) CRSS members, we are exploring software and system architecture evolution around the trend of Memory Disaggregation.
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Why CXL and Disaggregation?
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Microarchitecture Co-evolution with CXL (ISAs, Caches, PNM)
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Linux HMM scope, co-evolution with CXL, and limitations
Status
Current Stage
- Survey and Research Problem Definition
- Tracking industry developments and emerging requirements with industry participants
Next Up
- Measurement, Modeling and Simulation of Workloads and Systems with Disaggregated Memory
Publications
Last modified 18 Sep 2025

