CXL SIG (Disaggregated Memory)

In that open forum with current1 (and future2, hopefully) CRSS members, we are exploring software and system architecture evolution around the trend of Memory Disaggregation.

  • Why CXL and Disaggregation?

  • Microarchitecture Co-evolution with CXL (ISAs, Caches, PNM)

  • Linux HMM scope, co-evolution with CXL, and limitations

 

Status

Current Stage

  • Survey and Research Problem Definition
  • Tracking industry developments and emerging requirements with industry participants

Next Up

  • Measurement, Modeling and Simulation of Workloads and Systems with Disaggregated Memory

 

 

Publications

Last modified 18 Sep 2025